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M41T82 M41T83
Serial I2C bus RTC with battery switchover
Features

Ultra-low battery supply current of 365 nA Factory calibrated accuracy 5 ppm guaranteed after 2 reflows (SOX18) - Much better accuracies achievable using built-in programmable analog and digital calibration circuits 2.0 V to 5.5 V clock operating voltage Counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, year, and century Automatic switchover and reset output circuitry (fixed reference) - M41T83S VCC = 3.00 V to 5.50 V (2.85 V VRST 3.00 V) - M41T83R VCC = 2.70 V to 5.50 V (2.55 V VRST 2.70 V) - M41T83Z VCC = 2.38 V to 5.50 V (2.25 V VRST 2.38 V) Serial interface supports I C bus (400 kHz protocol) Programmable alarm with interrupt function (valid even during battery backup mode) Optional 2nd programmable alarm available Square wave output defaults to 32 KHz on power-up (M41T83 only) RESET (RST) output Watchdog timer Programmable 8-bit counter/timer 7 bytes of battery-backed user SRAM Battery low flag Power-down time stamp (HT bit) Low operating current of 80 A
2
18
QFN16, 4 mm x 4 mm (QA) (VFQFPN16)

1
SOX18 (18-pin, 300 mil SOIC with embedded crystal) (MY)
SO8 (M)

Oscillator stop detection Battery or SuperCapTM backup Operating temperature of -40 C to 85 C Package options include: - a 16-lead QFN (M41T83), - an 18-lead embedded crystal SOIC (M41T83), or - an 8-lead SOIC (M41T82) RoHS compliance: lead-free components are compliant with the RoHS directive

October 2010
Doc ID 12578 Rev 12
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www.st.com 1
Contents
M41T82-M41T83
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 2.3 2.4 2.5
Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Data retention and battery switchover (VSO = VRST) . . . . . . . . . . . . . . . . 18 Power-on reset (trec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 3.2 3.3 3.4 Power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Clock/control register map and divider chain . . . . . . . . . . . . . . . . . . . . . . 20 Real-time clock accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4.1 3.4.2 Digital calibration (periodic counter correction) . . . . . . . . . . . . . . . . . . . 26 Analog calibration (programmable load capacitance) . . . . . . . . . . . . . . 29
3.5 3.6 3.7 3.8
Setting the alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Optional second programmable alarm and user SRAM . . . . . . . . . . . . . . 34 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8-bit (countdown) timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.8.1 3.8.2 3.8.3 3.8.4 3.8.5 M41T83 timer interrupt/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Timer flag (TF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Timer interrupt enable (TIE, M41T83 only) . . . . . . . . . . . . . . . . . . . . . . 37 Timer enable (TE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 TD1/0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.9 3.10 3.11
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Square wave output (M41T83 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Century bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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Contents
3.12 3.13 3.14
Oscillator fail detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Oscillator fail interrupt enable (M41T83 only) . . . . . . . . . . . . . . . . . . . . . . 41 IRQ1/FT/OUT pin, frequency test, interrupts and the OUT bit (M41T83 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.14.1 3.14.2 Active mode operation on VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Backup mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.15 3.16 3.17
FT/RST pin, frequency test and reset output pin (M41T82 only) . . . . . . . 44 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 OTP bit operation (M41T83 in SOX18 package only) . . . . . . . . . . . . . . . 45
4 5 6 7 8 9
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
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List of tables
M41T82-M41T83
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 M41T82 clock/control register map (32 bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Key to Table 2: M41T82 clock/control register map (32 bytes). . . . . . . . . . . . . . . . . . . . . . 22 M41T83 clock/control register map (32 bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Key to Table 4: M41T83 clock/control register map (32 bytes). . . . . . . . . . . . . . . . . . . . . . 24 Digital calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Analog calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Watchdog register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Timer control register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Timer interrupt operation in free-running mode (with TI/TP = 1). . . . . . . . . . . . . . . . . . . . . 36 Timer source clock frequency selection (244.1 s to 4.25 hrs). . . . . . . . . . . . . . . . . . . . . . 37 Square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Century bits examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Priority for IRQ1/FT/OUT pin when operating on VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Priority for IRQ1/FT/OUT pin when operating in backup mode . . . . . . . . . . . . . . . . . . . . . 43 Initial power-on default values (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Initial power-up default values (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 QFN16 - 16-lead, quad, flat package, no lead, 4 x 4 mm pack. mech. data . . . . . . . . . . . 53 SOX18 - 18-lead plastic small outline, 300 mils, embedded crystal, package mech. data 55 SO8 - 8-lead plastic small outline (150 mils body width), package mech. data . . . . . . . . . 56 Carrier tape dimensions for QFN16, SOX18, and SO8 packages . . . . . . . . . . . . . . . . . . . 57 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
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List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. M41T82 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 M41T83 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SO8 (M) connections (M41T82) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 QFN16 (QA) connections (M41T83) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SOX18 (MY) connections (M41T83). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 M41T82 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 M41T82 hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 M41T83 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 M41T83 hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Alternative read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Internal load capacitance adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Clock accuracy vs. on-chip load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Clock divider chain and calibration circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Crystal isolation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Timer output waveform in free-running mode (with TI/TP = 1) . . . . . . . . . . . . . . . . . . . . . . 36 Battery check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 IRQ1/FT/OUT output pin circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Measurement AC I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 ICC2 vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Bus timing requirement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 QFN16 - 16-lead, quad, flat package, no lead, 4 x 4 mm body size outline . . . . . . . . . . . 53 QFN16 - 16-lead, quad, flat package, no lead, 4 x 4 mm, recommended footprint . . . . . . 54 32 KHz crystal + QFN16 vs. VSOJ20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SOX18 - 18-lead plastic small outline, 300 mils, embedded crystal, outline . . . . . . . . . . . 55 SO8 - 8-lead plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Carrier tape for QFN16, SOX18, and SO8 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
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Description
M41T82-M41T83
1
Description
The M41T8x are low power serial I2C real-time clocks with a built-in 32.768 kHz oscillator (external crystal-controlled for the QFN16 and SO8 packages, embedded crystal for the SOX18 package). Eight bytes of the register map (see Table 2 on page 21) are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. An additional 17 bytes of the register map provide status/control of the two alarms, watchdog, 8-bit counter, and square wave functions. An additional seven bytes are made available as user SRAM. Addresses and data are transferred serially via a two-line, bidirectional I2C interface. The built-in address register is incremented automatically after each WRITE or READ data byte. The M41T8x has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power failure occurs. The energy needed to sustain the clock operations can be supplied by a small lithium button battery when a power failure occurs. Functions available to the user include a non-volatile, time-of-day clock/calendar, two alarm interrupts, watchdog timer, programmable 8-bit counter, and square wave outputs. The eight clock address locations contain the century, year, month, date, day, hour, minute, second, and tenths/hundredths of a second in 24-hour BCD format. Corrections for 28, 29 (leap year), 30, and 31 day months are made automatically. The M41T83 is supplied in either a QFN16 (QA) or an SOX18 (MY), 300 mil SOIC which includes an embedded 32 KHz crystal. The SOX18 package requires only a user-supplied battery to provide non-volatile operation. The M41T82 is available only in an SO8 (M) package.
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M41T82-M41T83 Figure 1. M41T82 logic diagram
VBAT VCC
Description
XI XO SDA SCL (1) FT/RST
VSS
AI11196
1. Open drain
Figure 2.
M41T83 logic diagram
VBAT VCC
XI(1) XO(1) SDA SCL
SQW(2) IRQ1/OUT/FT(3) RST(3) IRQ2(3)
VSS
AI11195
1. For QFN16 package only 2. Defaults to 32 KHz on power-up 3. Open drain
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Description Table 1. Signal names
Description 32 KHz oscillator input 32 KHz oscillator output
(2)
M41T82-M41T83
Symbol XI(1) XO
(1)
IRQ1/OUT/FT SQW(3) RST FT/RST IRQ2(2) SDA SCL VBAT DU
(4)
Interrupt 1/output driver/frequency test output (open drain) 32 KHz programmable square wave output Power-on reset output (open drain) Frequency test output/power-on reset (open drain - M41T82 only) Interrupt for alarm 2 (open drain) Serial data address input/output Serial clock input Battery supply voltage (tie VBAT to VSS if no battery is connected.) Do not use Supply voltage Ground
VCC VSS
1. For SO8 and QFN16 packages only. 2. For SOX18 and QFN16 packages only. 3. Defaults to 32 KHz on power-up. 4. DU pin must be tied to VCC.
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M41T82-M41T83 Figure 3. SO8 (M) connections (M41T82)
XI XO VBAT VSS 1 2 3 4 8 7 6 5 VCC (1) FT/RST SCL SDA
Description
M41T82
AI11199
1. Open drain output
Figure 4.
QFN16 (QA) connections (M41T83)
XO VCC 14 NC 13 12 11 M41T83 NC SQW (2) 3 4 5 VBAT 6 VSS 7 NC 8 NC 10 9 SCL SDA IRQ2(1) (1) IRQ1/FT/OUT XI 15
16 RST(1) NC 1 2
AI11197
1. Open drain output. 2. Defaults to 32 KHz on power-up.
Figure 5.
SOX18 (MY) connections (M41T83)
NC (1) NF (1) NF NC (2) RST DU(3) (4) SQW VBAT VSS 1 2 3 4 5 6 7 8 9 18 17 16 15 M41T83 14 13 12 11 10 NC (1) NF NF(1) VCC IRQ2(2) NC (2) IRQ1/FT/OUT SCL SDA
AI11198
1. NF pins must be tied to VSS. Pins 2 and 3, and 16 and 17 are internally shorted together. 2. Open drain output. 3. Do not use (must be tied to VCC). 4. Defaults to 32 KHz on power-up.
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Description Figure 6. M41T82 block diagram
REAL TIME CLOCK CALENDAR OSCILLATOR FAIL CIRCUIT ALARM1 ALARM2 WATCHDOG I2C INTERFACE FT
M41T82-M41T83
XI CRYSTAL 32KHz OSCILLATOR XO
SDA
SCL WRITE PROTECT VCC < VRST
FREQUENCY TEST OUTPUT DRIVER 8-BIT COUNTER USER SRAM (7 Bytes)
INTERNAL POWER VCC
VBAT COMPARE trec TIMER
VRST/VSO(1)
RST (2)
AI11812
1. VRST = VSO = 2.93 V (S), 2.63 V (R), and 2.32 V (Z). 2. Open drain output.
Figure 7.
VCC
M41T82 hardware hookup
M41T82 VCC XI XO VBAT VSS SCL SDA (1) FT/RST VCC
MCU
Reset Input
Serial Clock Line Serial Data Line
AI11813
1. Open drain output.
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M41T82-M41T83 Figure 8. M41T83 block diagram
REAL TIME CLOCK CALENDAR OSCILLATOR FAIL CIRCUIT ALARM1 ALARM2 WATCHDOG IC INTERFACE SCL WRITE PROTECT VCC < VRST 2 FT OUT TIE SQWE OFIE A1IE A2IE
Description
XI CRYSTAL 32KHz OSCILLATOR XO
IRQ2(1) IRQ1/FT/OUT(1)
SDA
FREQUENCY TEST OUTPUT DRIVER 8-BIT COUNTER SQUARE WAVE 8 BITS OF OTP USER SRAM (7 Bytes)
SQW
INTERNAL POWER VCC
VBAT COMPARE trec TIMER
VRST/VSO(2)
RST(1)
AI11800
1. Open drain output. 2. VRST = VSO = 2.93 V (S), 2.63 V (R), and 2.32 V (Z).
Figure 9.
VCC
M41T83 hardware hookup
M41T83 VCC (1) IRQ1/FT/OUT XI (1) RST (1) XO IRQ2 VBAT VSS SCL SDA SQW VCC INT
MCU
Reset Input Port Serial Clock Line Serial Data Line 32KHz CLKIN
AI11801
1. Open drain output.
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Operation
M41T82-M41T83
2
Operation
The M41T8x clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 32 bytes contained in the device can then be accessed sequentially in the following order:

1st byte: tenths/hundredths of a second register 2nd byte: seconds register 3rd byte: minutes register 4th byte: century/hours register 5th byte: day register 6th byte: date register 7th byte: month register 8th byte: year register 9th byte: digital calibration register 10th byte: watchdog register 11th - 15th bytes: alarm 1 registers 16th byte: flags register 17th byte: timer value register 18th byte: timer control register 19th byte: analog calibration register 20th byte: square wave register 21st - 25th bytes: alarm 2 registers 26th - 32nd bytes: user RAM
The M41T8x clock continually monitors VCC for an out-of-tolerance condition. Should VCC fall below VRST, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from an out-of-tolerance system. The power input will also be switched from the VCC pin to the battery when VCC falls below the battery back-up switchover voltage (VSO = VRST). At this time the clock registers will be maintained by the attached battery supply. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC.
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M41T82-M41T83
Operation
2.1
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined:

Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line, while the clock line is high, will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
2.1.1
Bus not busy
Both data and clock lines remain high.
2.1.2
Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the START condition.
2.1.3
Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the STOP condition.
2.1.4
Data valid
The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition a device that gives out a message is called "transmitter," the receiving device that gets the message is called "receiver." The device that controls the message is called "master." The devices that are controlled by the master are called "slaves."
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Operation
M41T82-M41T83
2.1.5
Acknowledge
Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case the transmitter must leave the data line high to enable the master to generate the STOP condition. Figure 10. Serial bus data transfer sequence
DATA LINE STABLE DATA VALID
CLOCK
DATA
START CONDITION
CHANGE OF DATA ALLOWED
STOP CONDITION
AI00587
Figure 11. Acknowledgement sequence
START SCL FROM MASTER 1 2 8 CLOCK PULSE FOR ACKNOWLEDGEMENT 9
DATA OUTPUT BY TRANSMITTER
MSB
LSB
DATA OUTPUT BY RECEIVER
AI00601
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Operation
2.2
Read mode
In this mode the master reads the M41T8x slave after setting the slave address (see Figure 13 on page 16). Following the WRITE mode control bit (R/W = 0) and the acknowledge bit, the word address 'An' is written to the on-chip address pointer. Next the START condition and slave address are repeated followed by the READ mode control bit (R/W = 1). At this point the master transmitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter. The address pointer is only incremented on reception of an acknowledge clock. The M41T8x slave transmitter will now place the data byte at address An+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to An+2. This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter. Most of the registers and memory locations are accessed directly, but the RTC counters are accessed via a set of buffer/transfer registers at addresses 00h to 07h. The counters are not directly read nor written. Instead, at the start of a read or write cycle, the counters are copied into the eight buffer/transfer registers so that the user can read them out sequentially, receiving a coherent set of data, copied from the same instant in time. An alternate READ mode may also be implemented whereby the master reads the M41T8x slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure 14 on page 16). Figure 12. Slave address location
R/W
START
SLAVE ADDRESS
A
MSB
1
1
0
1
0
0
LSB 0
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Operation Figure 13. Read mode sequence
START START R/W BUS ACTIVITY: MASTER R/W
M41T82-M41T83
SDA LINE
S
WORD ADDRESS (An) ACK
S
DATA n
DATA n+1
ACK
ACK
ACK
BUS ACTIVITY: SLAVE ADDRESS
SLAVE ADDRESS STOP
DATA n+X
P
NO ACK
ACK
AI00899
Figure 14. Alternative read mode sequence
START BUS ACTIVITY: MASTER SDA LINE R/W STOP DATA n ACK ACK DATA n+1 ACK ACK DATA n+X P NO ACK
S
BUS ACTIVITY: SLAVE ADDRESS
AI00895
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Operation
2.3
Write mode
In this mode the master transmitter transmits to the M41T8x slave receiver. Bus protocol is shown in Figure 15. Following the START condition and slave address, a logic 0 (R/W = 0) is placed on the bus and indicates to the addressed device that word address "An" will follow and is to be written to the on-chip address pointer. The data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next address location on the reception of an acknowledge clock. The M41T8x slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address see Figure 12 on page 15 and again after it has received the word address and each data byte.
Figure 15. Write mode sequence
START STOP WORD ADDRESS (An) ACK ACK DATA n DATA n+1 DATA n+X P ACK ACK ACK
AI00591
BUS ACTIVITY: MASTER
SDA LINE
S
BUS ACTIVITY: SLAVE ADDRESS
As in the case of reading, some registers and memory locations are written directly, but the RTC counters are written via a set of eight buffer/transfer registers at addresses 00h to 07h. The user will write the date and time information sequentially, and then, at the end of the I2C write cycle or when the address pointer increments beyond 07h, the buffer/transfer registers will be copied into the RTC counters. All the time parameters - fractions, seconds, minutes, hours, day, date, month, year, and century bits - are copied simultaneously. Whatever value is in the buffer/transfer registers will be copied to the counters, so if the user only changes one of the eight bytes, the remaining seven bytes will receive the unchanged contents of the buffer/transfer registers, which will contain whatever was in the counters at the start of the write access. For example, if the user starts a write cycle on Monday, November 16, 2009, at 17:52:27.03, and writes a 22 to the minutes registers, the value Monday, November 16, 2009, 17:52:22.03 will be written back into the counters. At the start of the write cycle, the eight bytes of counters were copied into the buffer/transfer registers. Then, the seconds register was overwritten. Finally, the eight bytes were copied back into the counters with the result that the seconds value was changed.
R/W
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Operation
M41T82-M41T83
2.4
Data retention and battery switchover (VSO = VRST)
Once VCC falls below the switchover voltage (VSO = VRST), the device automatically switches over to the battery and powers down into an ultra low current mode of operation to preserve battery life. If VBAT is less than, or greater than VRST, the device power is switched from VCC to VBAT when VCC drops below VRST (see Figure 26 on page 50). At this time the clock registers and user RAM will be maintained by the attached battery supply. When it is powered back up, the device switches back from battery to VCC at VSO + hysteresis. When VCC rises above VRST, it will recognize the inputs. For more information on battery storage life refer to Application Note AN1012.
2.5
Power-on reset (trec)
The M41T8x continuously monitors VCC. When VCC falls to the power fail detect trip point, the RST output pulls low (open drain) and remains low after power-up for trec (210 ms typical) after VCC rises above VRST (max).
Note:
The trec period does not affect the RTC operation. Write protect only occurs when VCC is below VRST. When VCC rises above VRST, the RTC will be selectable immediately. Only the RST output is affected by the trec period. The RST pin is an open drain output and an appropriate pull-up resistor to VCC should be chosen to control the rise time.
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M41T82-M41T83
Clock operation
3
Clock operation
The M41T8x is driven by a quartz-controlled oscillator with a nominal frequency of 32.768 kHz. The accuracy of the real-time clock depends on the frequency of the quartz crystal that is used as the time-base for the RTC. The 8-byte clock register (see Table 2 on page 21 and Table 4 on page 23) is used to both set the clock and to read the date and time from the clock, in binary coded decimal format. Tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first four registers. Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause the oscillator to stop. When reset to a 0 the oscillator restarts within one second (typical).
Note:
Upon initial power-up, the user should set the ST bit to a '1,' then immediately reset the ST bit to 0. This provides an additional "kick-start" to the oscillator circuit. Bits D6 and D7 of clock register 03h (century/ hours register) contain the CENTURY bit 0 (CB0) and CENTURY bit 1 (CB1). Bits D0 through D2 of register 04h contain the day (day of week). Registers 05h, 06h, and 07h contain the date (day of month), month, and years. The ninth clock register is the digital calibration register, while the analog calibration register is found at address 12h (these are both described in Section 3.4: Clock calibration). The RTC includes an oscillator fail detect circuit which sets the OF bit in the flags register (bit 2, register 0fh). For the M41T83, bit D7 of register 09h (watchdog register) contains the oscillator fail interrupt enable bit (OFIE) which can be used to enable an interrupt when the OF bit is set (see Section 3.12: Oscillator fail detection on page 40) will also generate an interrupt output.
Note:
A WRITE to ANY location within the first eight bytes of the clock register (00h-07h), including the ST bit and CB0-CB1 bits will result in an update of the RTC counters and a reset of the divider chain. This could result in an inadvertent change of the current time. For example, the ST bit is in the seconds register (address 01h) and the century bits (CB0-CB1) are in the hours register (address 03h), so the user should take care to not alter these other parameters when changing the ST bit or the century bits. The eight clock registers may be read one byte at a time or in a sequential block. At the start of a read cycle, a copy of the time/date counters is placed in the buffer/transfer registers and can then be transferred out sequentially without concern that the time/date increments during the transfer and thus yields a corrupt value. For example, if the user were to read the seconds register, then start another bus cycle to read the minutes register, the minutes counter could have incremented during the time between the two read cycles. The seconds and minutes values would not be from the same instant in time; they would not be coherent. By using the sequential read feature, the values shifted out are from the same instant in time and are thus coherent. Similarly, when writing to the RTC registers, during one write cycle, the user can sequentially transfer all eight bytes of time/date into the buffer/transfer registers whereupon they will be loaded simultaneously into the RTC counters thus ensuring a coherent update of the time/date.
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Clock operation
M41T82-M41T83
3.1
Power-down time-stamp
When a power failure occurs, the time/date counters are copied into the buffer/transfer registers and the halt update bit (HT) is automatically set to a "1". The HT bit prevents the normal copying from counters to registers which occurs at the start of a read or write cycle. Thus, upon power-up, the user can read the RTC registers to ascertain the time of powerdown. Additional reads will return the same time. It will appear to be frozen until the HT bit (D6, address 0Ch) is written to 0 by the user. Then, subsequent reads will then return the current time. For more information, see application notes AN1572 and AN3060.
Note:
Writes to the RTC registers (addresses 00h to 07h) with the HT bit set can cause time corruption. Example: Assume a power-fail time of Monday, November 16, 2009, at 17:52:27.03. At the next power-up, that time will be frozen in the buffer/transfer registers. On November 17, 2009, at 16:15:07.77, the user powers the system back up and tries to write the seconds to 35 while the HT bit is still set. This will cause Monday, November 16, 2009, at 17:52:35.03 to be written into the counters because the other seven bytes of buffer/transfer register still contain the time of power-down. The result is that the modified time of power-down was written into the counters making it appear the part had lost time while power was off. Thus, at power-up, the user should always clear the HT bit (write D6 to 0 in address 0Ch) before writing to any address in the range 00h to 07h. A typical power-up flow is to read the time of power-down, then clear the HT bit, then read the current time. If the time of power-down is not needed by the application, then the first step can be omitted.
3.2
Clock/control register map and divider chain
The M41T8x is comprised of 32 addresses which contain registers for clock (time and date), calibration (digital and analog), alarm 1 and 2, watchdog, flags, timer, and square wave (M41T83 only). Clock and alarm registers store data in BCD format. Calibration, timer, watchdog, and square wave bits are written in a binary format. Whenever any of the eight RTC bytes (addresses 00h to 07h) are written, the internal divider (or clock) chain will be reset upon the completion of the write cycle.
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M41T82-M41T83 Table 2.
Addr D7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h-1Fh TE ACS 0 0
(3)
Clock operation
M41T82 clock/control register map (32 bytes)(1)
Function/range BCD format seconds seconds minutes Century/hours Day Date Month Year DC0 RB0 Digital calibration Watchdog Al1 month Al1 date Al1 hour Al1 min Al1 sec 0 Flags Timer value 0 AC2 0 TD1 AC1 AL2E TD0 AC0 0 Timer control Analog calibration SQW SRAM/Al2 month SRAM/Al2 date SRAM/Al2 hour SRAM/Al2 min SRAM/Al2 sec SRAM 01-12 01-31 00-23 00-59 00-59 01-12 01-31 00-23 00-59 00-59 00-99 00-59 00-59 0-3/00-23 01-7 01-31 01-12 00-99
D6
D5
D4
D3
D2
D1
D0
0.1 seconds ST 0 CB1 0 0 0 CB0 0 0 0 0 10 years 0 0 0 RPT14 RPT13 RPT12 RPT11 WDF FT BMB4 0 RPT15 HT DCS BMB3 ABE DC4 BMB2 Al1 10M DC3 BMB1 0 10 date 10M 10 seconds 10 minutes 10 hours 0 0
0.01 seconds seconds minutes Hours (24 hour format) Day of week Date: day of month Month Year DC2 BMB0 DC1 RB1
Alarm1 month Alarm1 date Alarm1 hour Alarm1 minutes Alarm1 seconds TF OF 0
AI1 10 date AI1 10 hour
Alarm1 10 minutes Alarm1 10 seconds AF1 AF2
(2)
BL
Timer countdown value 0 AC6 0 0(3) RPT25 0(3) 0 AC5 0 0(3) 0 AC4 0 Al2 10M 0 AC3 0
Alarm2 month Alarm2 month Alarm2 date Alarm2 minutes Alarm2 seconds
RPT24 RPT23 RPT22 RPT21
AI2 10 date AI2 10 hour
Alarm2 10 minutes Alarm2 10 seconds User SRAM (7 bytes)
1. See Table 3: Key to Table 2: M41T82 clock/control register map (32 bytes) 2. AF2 will always read 0, if the AL2E bit is set to 0. 3. As indicated in Table 3, the 0 bits should be written to 0. But in the case of these four bits, when AL2E is 0, registers 14-18h are SRAM locations and these bits become SRAM cells which are thus excluded from that restriction.
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Clock operation Table 3.
M41T82-M41T83 Key to Table 2: M41T82 clock/control register map (32 bytes)
Code Explanation Must be set to zero Alarm in battery backup enable bit Analog calibration bits Analog calibration sign bit Alarm flag bits Alarm 2 enable bit Battery low bit Watchdog multiplier bits Century bits Digital calibration bits Digital calibration sign bit Frequency test bit Halt update bit Oscillator fail bit Watchdog resolution bits Alarm 1 repeat mode bits Alarm 2 repeat mode bits Stop bit Timer frequency bits Timer enable bit Timer flag Watchdog flag
0 ABE AC0-AC6 ACS AF1, AF2 AL2E BL BMB0-BMB4 CB0, CB1 DC0-DC4 DCS FT HT OF RB0-RB2 RPT11-RPT15 RPT21-RPT25 ST TD0, TD1 TE TF WDF
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M41T82-M41T83 Table 4.
Addr D7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h1Fh TE ACS RS3 A2IE RPT24 RPT23 RPT22 RPT21 TI/TP AC6 RS2 0(3) RPT25 0
(3)
Clock operation
M41T83 clock/control register map (32 bytes)(1)
Function/range BCD format seconds seconds Minutes Century/hours Day Date Month Year DC1 RB1 DC0 RB0 Digital calibration Watchdog Al1 month Al1 date Al1 hour Al1 min Al1 sec 0 Flags Timer value 0 AC2 0 TD1 AC1 AL2E TD0 AC0 OTP Timer control Analog calibration SQW SRAM/Al2 month SRAM/Al2 date SRAM/Al2 hour SRAM/Al2 min SRAM/Al2 sec SRAM 01-12 01-31 00-23 00-59 00-59 01-12 01-31 00-23 00-59 00-59 00-99 00-59 00-59 0-3/00-23 01-7 01-31 01-12 00-99
D6
D5
D4
D3
D2
D1
D0
0.1 seconds ST 0 CB1 0 0 0 CB0 0 0 0 0 10 seconds 10 minutes 10 hours 0 10 date 10M 0 0
0.01 seconds seconds Minutes Hours (24 hour format) Day of week Date: day of month Month Year DC4 BMB2 Al1 10M DC3 BMB1 DC2 BMB0
10 years OUT OFIE A1IE RPT14 RPT13 RPT12 RPT11 WDF FT BMB4 SQWE RPT15 HT DCS BMB3 ABE
Alarm 1month Alarm1 date Alarm1 hour Alarm1 minutes Alarm1 seconds TF OF 0
AI1 10 date AI1 10 hour
Alarm1 10 minutes Alarm1 10 seconds AF1 AF2(2) BL
Timer countdown value TIE AC5 RS1 0(3) 0 AC4 RS0 Al2 10M 0 AC3 0
Alarm2 month Alarm2 date Alarm2 hour Alarm2 minutes Alarm2 seconds
AI2 10 date AI2 10 hour
Alarm2 10 minutes Alarm2 10 seconds User SRAM (7 bytes)
1. See Table 5: Key to Table 4: M41T83 clock/control register map (32 bytes). 2. AF2 will always read 0, if the AL2E bit is set to 0. 3. As indicated in Table 5, the 0 bits should be written to 0. But in the case of these three bits, when AL2E is 0, registers 14-18h are SRAM locations and these bits become SRAM cells which are thus excluded from that restriction.
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Clock operation Table 5.
M41T82-M41T83 Key to Table 4: M41T83 clock/control register map (32 bytes)
Code Explanation Must be set to zero Alarm in battery back-up enable bit Alarm interrupt enable bits Analog calibration bits Analog calibration sign bit Alarm flag Alarm 2 enable bit Battery low bit Watchdog multiplier bits Century bits Digital calibration bits Digital calibration Sign bit Frequency test bit Halt update bit Oscillator fail bit Output level Oscillator fail interrupt enable OTP control bit Watchdog resolution bits Alarm 1 repeat mode bits Alarm 2 repeat mode bits SQW frequency Square wave enable SRAM/alarm 2 bit Stop bit Timer frequency bits Timer enable bit Timer flag Timer interrupt or pulse Timer interrupt enable Watchdog flag
0 ABE A1IE, A2IE AC0-AC6 ACS AF1, AF2 AL2E BL BMB0-BMB4 CB0, CB1 DC0-DC4 DCS FT HT OF OUT OFIE OTP RB0-RB2 RPT11-RPT15 RPT21-RPT25 RS0-RS3 SQWE SRAM/ALM2 ST TD0, TD1 TE TF TI/TP TIE WDF
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Clock operation
3.3
Real-time clock accuracy
The M41T8x is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The accuracy of the real-time clock is dependent upon the accuracy of the crystal, and the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Temperature also affects the crystal frequency, causing additional error (see Figure 17 on page 30). The M41T8x provides the option of clock correction through either manufacturing calibration or in-application calibration. The total possible compensation is typically -93 ppm to +156 ppm. The two compensation circuits that are available are: 1. An analog calibration register (12h) can be used to adjust internal (on-chip) load capacitors for oscillator capacitance trimming. The individual load capacitors CXI and CXO (see Figure 16), are selectable from a range of -18 pF to +9.75 pF in steps of 0.25 pF. This translates to a calculated compensation of approximately 30 ppm (see Section 3.4.2: Analog calibration (programmable load capacitance) on page 29). A digital calibration register (08h) can also be used to adjust the clock counter by adding or subtracting a pulse at the 512 Hz divider stage. This approach provides periodic compensation of approximately -63 ppm to +126 ppm (see Section 3.4.1: Digital calibration (periodic counter correction) on page 26).
2.
Figure 16. Internal load capacitance adjustment
XI CXI Crystal Oscillator XO CXO
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Clock operation
M41T82-M41T83
3.4
Clock calibration
The M41T8x oscillator is designed for use with a 12.5 pF crystal load capacitance. When the calibration circuit is properly employed, accuracy improves to better than 1 ppm at 25 C. The M41T8x design provides the following two methods for clock error correction.
3.4.1
Digital calibration (periodic counter correction)
This method employs the use of periodic counter correction by adjusting the ratio of the 100 Hz divider stage to the 512 Hz divider stage. Under normal operation, the 100 Hz divider stage outputs precisely 100 pulses for every 512 pulses of the 512 Hz input stage to provide the input frequency to the fraction of seconds clock register. By adjusting the number of 512 Hz input pulses used to generate 100 output pulses, the clock can be sped up or slowed down, as shown in Figure 19 on page 32. When a non-zero value is loaded into the five calibration bits (DC4 - DC0) found in the digital calibration register (08h) and the sign bit is 1, (indicating positive calibration), the 100 Hz stage outputs 100 pulses for every 511 input pulses instead of the normal 512. Since the 100 pulses are now being output in a shorter window, this has the effect of speeding up the clock by 1/512 seconds for each second the circuit is active. Similarly, when the sign bit is 0, indicating negative calibration, the block outputs 100 pulses for every 513 input pulses. Since the 100 pulses are then being output in a longer window, this has the effect of slowing down the clock by 1/512 seconds for each second the circuit is active. The amount of calibration is controlled by using the value in the calibration register (N) to generate the adjustment in one second increments. This is done for the first N seconds once every eight minutes for positive calibration, and for N seconds once every sixteen minutes for negative calibration (see Table 6 on page 28). For example, if the calibration register is set to 100010, then the adjustment will occur for two seconds in every minute. Similarly, if the calibration register is set to 000011, then the adjustment will occur for 3 seconds in every alternating minute. The digital calibration bits (DC4 - DC0) occupy the five lower order bits in the digital calibration register (08h). These bits can be set to represent any value between 0 and 31 in binary form. The sixth bit (DCS) is a sign bit; 1 indicates positive calibration, 0 indicates negative calibration. Calibration occurs within an 8-minute (positive) or 16-minute (negative) cycle. Therefore, each calibration step has an effect on clock accuracy of +4.068 or -2.034 ppm. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or -5.35 seconds per month, which corresponds to a total range of +5.5 or -2.75 minutes per month. One method of determining the amount of digital calibration required is to use the frequency test output (FT) of the device (see Section 3.14: IRQ1/FT/OUT pin, frequency test, interrupts and the OUT bit (M41T83 only) on page 41 for more information on enabling the FT output). When FT is enabled, a 512 Hz signal is output in the IRQ1/FT/OUT pin on the M41T83, and on the FT/RST pin on the M41T82. This signal can be measured using a highly accurate timing device such as a frequency counter. The measured value is then compared to 512 Hz and the oscillator error in ppm is then determined. The user should keep in mind that changes in the digital calibration value will not affect the signal measured on the FT pin. While the analog calibration circuit does affect the oscillator,
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Clock operation
the digital calibration circuitry uses periodic counter correction which occurs downstream of the 512 Hz divider chain and hence has no effect on the FT pin. Note: 1 The modified pulses are not observable on the frequency test (FT) output, nor will the effect of the calibration be measurable real-time, due to the periodic nature of the error compensation. Positive digital calibration is performed on an eight minute cycle, therefore the value in the calibration register should not be modified more frequently than once every eight minutes for positive values of calibration. Negative digital calibration is performed on a sixteen minute cycle, therefore negative values in the calibration register should not be modified more frequently than once every sixteen minutes.
2
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Clock operation Table 6. Digital calibration values
M41T82-M41T83
Calibration value (binary) DC4 - DC0 0 (00000) 1 (00001) 2 (00010) 3 (00011) 4 (00100) 5 (00101) 6 (00110) 7 (00111) 8 (01000) 9 (01001) 10 (01010) 11 (01011) 12 (01100) 13 (01101) 14 (01110) 15 (01111) 16 (10000) 17 (10001) 18 (10010) 19 (10011) 20 (10100) 21 (10101) 22 (10110) 23 (10111) 24 (11000) 25 (11001) 26 (11010) 27 (11011) 28 (11100) 29 (11101) 30 (11110) 31 (11111)
Calibration value rounded to the nearest ppm Negative calibration (DCS = 0) Positive calibration (DCS = 1) to speed up a slow clock to slow a fast clock 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -22 -24 -26 -28 -31 -33 -35 -37 -39 -41 -43 -45 -47 -49 -51 -53 -55 -57 -59 -61 -63 0 4 8 12 16 20 24 28 33 37 41 45 49 53 57 61 65 69 73 77 81 85 90 94 98 102 106 110 114 118 122 126
N
N/491520 (per minute)
N/245760 (per minute)
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Clock operation
3.4.2
Analog calibration (programmable load capacitance)
A second method of calibration employs the use of programmable internal load capacitors to adjust (or trim) the oscillator frequency. As discussed in Section 3.4.1, the 512 Hz frequency test output can be used to determine the amount of frequency error in the oscillator. Changes in the analog calibration value will affect the frequency test output, thus the user can immediately see the effects of these changes (see Section 3.14 on page 41 for more information on enabling the FT output). By design, the oscillator is intended to be 0 ppm crystal accuracy at room temperature (25 C, see Figure 17 on page 30). For a 12.5 pF crystal, the default loading on each side of the crystal will be 25 pF. For incrementing or decrementing the calibration value, capacitance will be added or removed in increments of 0.25 pF to each side of the crystal. Internally, CLOAD of the oscillator is changed via two digitally controlled capacitors, CXI and CXO, connected from the XI and XO pins to ground (see Figure 16 on page 25). The effective on-chip series load capacitance, CLOAD, ranges from 3.5 pF to 17.4 pF, with a nominal value of 12.5 pF (AC0 - AC6 = 0). The effective series load capacitance (CLOAD) is the combination of CXI and CXO: C LOAD = 1 ( 1 C XI + 1 C XO ) Seven analog calibration bits, AC0 to AC6, are provided in order to adjust the on-chip load capacitance value for frequency compensation of the RTC. Each bit has a different weight for capacitance adjustment. An analog calibration sign (ACS) bit determines if capacitance is added (ACS bit = 0, negative calibration) or removed (ACS bit = 1, positive calibration). The majority of the calibration adjustment is positive (i.e. to increase the oscillator frequency by removing capacitance) due to the typical characteristic of quartz crystals to slow down due to changes in temperature, but negative calibration is also available. Since the analog calibration register adjustment is essentially pulling the frequency of the oscillator, the resulting frequency changes will not be linear with incremental capacitance changes. The equations which govern this mechanism indicate that smaller capacitor values of analog calibration adjustment will provide larger increments. Thus, the larger values of analog calibration adjustment will produce smaller incremental frequency changes. These values typically vary from 6-10 ppm/bit at the low end to <1 ppm/bit at the highest capacitance settings. The range provided by the analog calibration register adjustment with a typical surface mount crystal is approximately 30 ppm around the AC6-AC0 = 0 default setting because of this property (see Table 7 on page 30).
Pre-programmed calibration value
Users of the M41T83 in the embedded crystal package have the option of using the factory programmed analog calibration value (refer to Section 3.17: OTP bit operation (M41T83 in SOX18 package only) on page 45).
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Clock operation Figure 17. Crystal accuracy across temperature
Frequency (ppm) 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 F = K x (T - T )2 O F
2 2 K = -0.036 ppm/C 0.006 ppm/C
M41T82-M41T83
TO = 25C 5C
Temperature C
AI07888
Table 7.
Analog calibration values
D7 D6 D5 D4 D3 D2 D1 D0 CXI, CXO CLOAD(1)
Addr
Analog calibration value
ACS () 0 pF 3 pF 5 pF 12h -7 pF 9.75 pF(2) -18 pF
(3)
AC6
AC5
AC4
AC3
AC2
AC1
AC0
(16 pF) (8 pF) 0 0 0 0 0 1 0 0 0 0 1 0
(4 pF) (2 pF) (1 pF) (0.5 pF) (0.25 pF) 0 0 1 1 0 0 0 1 0 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 25 pF 28 pF 30 pF 18 pF 34.75 pF 7 pF
1/2(CXI, CXO) 12.5 pF 14 pF 15 pF 9 pF 17.4 pF 3.5 pF
x 0 0 1 0 1
1. CLOAD = 1/(1/CXI + 1/CXO). 2. Maximum negative calibration value. 3. Maximum positive calibration value.
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M41T82-M41T83 The on-chip capacitance can be calculated as follows:
CLOAD = 1 [ ACS (AC6 : AC0 value, decimal) 0.25+ 25]pF 2
Clock operation
where ACS is the sign. For example:

CLOAD (12h = x0000000) = 12.5 pF CLOAD (12h =11001000) = 3.5 pF (sign is negative) CLOAD (12h = 00100111) = 17.4 pF
With the analog calibration adjusted to its lowest value, the oscillator will see a minimum of 3.5 pF load capacitance as shown on the bottom row of Table 7. Note: These are typical values, and the total load capacitance seen by the crystal will include approximately 1-2 pF of package and board capacitance in addition to the analog calibration register value. Any invalid value of analog calibration will result in the default capacitance of 25 pF. The combination of analog and digital trimming can give up to -93 to +156 ppm of the total adjustment. Figure 18 represents a typical curve of clock ppm adjustment versus the analog calibration value. This curve may vary with different crystals, so it is good practice to evaluate the crystal to be used with an M41T8x device before establishing the adjustment values for the application in question. Figure 18. Clock accuracy vs. on-chip load capacitance
100.0
XI XO Crystal Oscillator
80.0
PPM ADJUSTMENT
60.0 40.0
CXI
CXO
CLOAD =
20.0
FASTER DECREASING LOAD CAP.
CXI * CXO CXI + CXO
On-Chip
INCREASING LOAD CAP.
0.0
SLOWER
-20.0 OFFSET TO CXI, CXO (pF) NET EQUIV. LOAD CAP., C LOAD, (pF) Analog Calibration Value, AC, register 0x12 -18.0 -15.0 3.5 5.0 -10.0 7.5 0xA8 -5.0 10 0x94 0.0 12.5 0x00 5.0 15 0x14 9.75 17.4 0x27
ai13906
0xC8 0xBC
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Clock operation
M41T82-M41T83
Two methods are available for ascertaining how much calibration a given M41T8x may require:
The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses either or both of the calibration bytes. The second approach is better suited to a manufacturing environment, and uses the 512 Hz frequency test output. This is the IRQ1/FT/OUT pin on the M41T83, and the FT/RST pin on the M41T82 (see Section 3.14 and Section 3.15 for more information on enabling the FT output). The 512 Hz frequency test signal can be measured using a highly accurate timing device such as a frequency counter. The measured value is then compared to 512 Hz and the oscillator error in ppm is then determined. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm oscillator frequency error, requiring either a -10 (xx001010) to be loaded into the digital calibration byte, or +6 pF (00011000) into the analog calibration byte for correction.
Note:
Setting or changing the digital calibration byte does not affect the frequency test, square wave, or watchdog timer frequency, but changing the analog calibration byte DOES affect all functions derived from the low current oscillator (see Figure 19).
Figure 19. Clock divider chain and calibration circuits
512Hz Output Frequency Test /64 CXI 32KHz Low Current Oscillator /64 CXO Digital Calibration Circuitry (divide by 511/512/513) 1Hz Signal Analog Calibration Circuitry Clock Counters /2 Remainder of Divider Circuit Square Wave Watchdog Timer 8-bit Timer
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M41T82-M41T83 Figure 20. Crystal isolation example
Crystal Local Grounding Plane (Layer 2)
Clock operation
XI XO
VSS
AI11814
1. Substrate pad should be tied to VSS.
3.5
Setting the alarm clock registers
Codes not listed in the table default to the once-per-second mode to quickly alert the user of an incorrect alarm setting. When the clock information matches the alarm clock settings based on the match criteria defined by RPTx5-RPTx1 (x = 1 for alarm 1 or 2 for alarm 2), the alarm flag, AFx, is set. Reading the flags register clears the alarm flags. A subsequent read of the flags register is necessary to see that the value of the alarm flag has been reset to 0.
M41T83 interrupts on alarm
In the M41T83, for alarm 1, setting the alarm interrupt enable, A1IE, allows an interrupt output to be asserted upon AF1 being set provided that other configuration bits are set accordingly (see Section 3.14 for more information on the IRQ/FT/OUT output). Likewise for alarm 2, with A2IE set, IRQ2 will be asserted upon AF2 going high. To disable either of the alarms, write a 0 to the alarm date registers and to the RPTx5-RPTx1 bits. Note: If the address pointer is allowed to increment to the flag register address, or the last address written is "Alarm Seconds," the address pointer will increment to the flag address, and an alarm condition will not cause the interrupt/flag to occur until the address pointer is moved to a different address. Alarm IRQ outputs are de-asserted when the alarm flags are cleared by reading the flags register (0Fh). The IRQ1/FT/OUT pin can also be activated in the battery backup mode. This requires the ABE bit (alarm in backup enable) to be set (see Section 3.14.2: Backup mode for additional conditions which apply). Once an interrupt is asserted in backup mode, it will remain true until VCC is restored and a subsequent read of the flags register occurs.
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Clock operation
M41T82-M41T83
3.6
Optional second programmable alarm and user SRAM
When the alarm 2 enable (AL2E) bit (D1 of address 13h) is set to a logic 1, registers 14h through 18h provide control for a second programmable alarm which operates in the same manner as the alarm function described in Section 3.5. The AL2E bit defaults on initial power-up to a logic 0 (alarm 2 disabled). In this mode, the five alarm 2 bytes (14h-18h) function as additional user SRAM, for a total of 12 bytes of user SRAM. With AL2E set to 1, the alarm is enabled, and will cause the AF2 bit to be set when the alarm condition is met. On the M41T83, if the A2IE (alarm 2 interrupt enable) bit is set, an interrupt will be asserted on IRQ2. The interrupt is de-asserted when the alarm flags are cleared by reading the flags register (0Fh). IRQ2 can be enabled in backup mode by setting ABE to 1 (in conjuction with setting A2IE). Table 8.
RPT5 1 1 1 1 1 0
Alarm repeat modes
RPT4 1 1 1 1 0 0 RPT3 1 1 1 0 0 0 RPT2 1 1 0 0 0 0 RPT1 1 0 0 0 0 0 Alarm setting Once per second Once per minute Once per hour Once per day Once per month Once per year
3.7
Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the two lower order bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (For example: writing 00001110 in the watchdog register = 3*1, or 3 seconds). If the processor does not reset the timer within the specified period, the M41T8x sets the WDF (watchdog flag). The watchdog timer is reset by writing to the watchdog register. The time-out period then starts over.
M41T83 watchdog interrupt
On the M41T83, provided that the necessary configuration bits are set, the IRQ/FT/OUT output will be asserted when the watchdog times out (see Section 3.14 for additional conditions which apply). Should the watchdog time out, to de-assert the IRQ1/FT/OUT output, the lower seven bits of the watchdog register (09h) must be written. This will de-assert the output and re-initialize the watchdog. Writing these seven bits to 0 will de-assert the output and disable the watchdog.
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Clock operation
A READ of the flags register will reset the watchdog flag (bit D7; register 0Fh) but not deassert the IRQ1/FT/OUT output. The watchdog function is automatically disabled upon power-up and the watchdog register is cleared. Table 9.
Addr 09h
Watchdog register
D7 OFIE D6 BMB4 D5 BMB3 D4 BMB2 D3 BMB1 D2 BMB0 D1 RB1 D0 RB0 Function Watchdog
3.8
8-bit (countdown) timer
The timer value register is an 8-bit binary countdown timer. It is enabled and disabled via the timer control register (11h) TE bit. Other timer properties such as the source clock, or interrupt generation are also selected in the timer control register (see Table 10). For accurate read back of the countdown value, the I2C-bus clock (SCL) must be operating at a frequency of at least twice the selected timer clock. The timer control register selects one of four source clock frequencies for the timer (4096, 64, 1, or 1/60 Hz), and enables/disables the timer. The timer counts down from a softwareloaded 8-bit binary value (register 10h) and decrements to 1. On the next tick of the counter, it reloads the timer countdown value and sets the timer flag (TF) bit. The TF bit can only be cleared by software. When asserted, the timer flag (TF) can also be used to generate an interrupt (IRQ1/FT/OUT) on the M41T83. Writing the timer countdown value (10h) has no effect on the TF bit or the IRQ1/FT/OUT output.
3.8.1
M41T83 timer interrupt/output
On the M41T83, there are two choices for the output depending on the TI/TP configuration bit (timer interrupt/timer pulse, bit 6, register 11h).
Normal interrupt mode
With TI/TP = 0, the output will assert like a normal interrupt, staying low until the TF bit is cleared by software by reading the flags register (0Fh).
Free-running mode
When TI/TP is a 1, the output is a free-running waveform as depicted in Figure 21. After being low for the specified time (as shown in Table 11), the output automatically goes high without need of software clearing any bits. The TF bit will still be set each time the timer reloads, but it is not necessary for the software to clear it in this mode. Furthermore, clearing the TF bit has no effect on the output in this mode. While writes to the timer countdown register (10h) control the reload value, reads of this register return the current countdown timer value.
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Clock operation Table 10.
Addr 0Fh 10h 11h TE TI/TP
M41T82-M41T83 Timer control register map(1)
D7 WDF D6 AF1 D5 AF2 D4 BL D3 TF D2 OF
(2)
D1 0
D0 0
Function Flags Timer value
Timer countdown value TIE 0 0
0
TD1
TD0
Timer control
1. Bit positions labeled with 0 should always be written with logic 0. 2. Writing to the timer register will not reset the TF bit nor clear the interrupt.
When the timer is in the free-running mode, with a value of n programmed into the timer countdown value, the output will nominally be low for one cycle of the specified clock source and high for n-1 cycles with an overal period of n cycles. Thus, the countdown period is n/source clock frequency. For the special case of n = 1, as shown in Table 11, when the clock source is 4096 or 64 Hz, the low time (TL) is half the clock period instead of a full clock period. Table 11. Timer interrupt operation in free-running mode (with TI/TP = 1)
IRQ low time - TL (seconds)(1) Source clock (Hz) 4096 64 1 1/60 n = 1(2) n>1 IRQ period - TIRQ (seconds) n=1 1/4096 = 244 s 1/64 = 15.6 ms 1 1 minute n>1 n / 4096 n / 64 n n minutes
1/8192 = 122 s 1/4096 = 244 s 1/128 = 7.8 ms 1/64 1/64 1/64 = 15.6 ms 1/64 1/64
1. IRQ1/FT/OUT is asserted coincident with TF going true. 2. n = loaded countdown timer value (0 < n < 255). The timer is stopped when n = 0.
Figure 21. Timer output waveform in free-running mode (with TI/TP = 1)
TIRQ TL
IRQ1/FT/OUT
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Clock operation
3.8.2
Timer flag (TF)
At the end of a timer countdown, when the timer reloads, TF is set to logic '1.' Regardless of the state of TF bit (or TI/TP bit), the timer will continue decrementing and reloading. If both timer and alarm interrupts are used in the application, the source of the interrupt can be determined by reading the flag bits. Refer to Section 3.14 for more information on the interaction of these bits. The TF bit is cleared by reading the flags register. This will deassert an interrupt output due to the timer.
3.8.3
Timer interrupt enable (TIE, M41T83 only)
In normal interrupt mode (TI/TP = 0), when TF is asserted, the interrupt output is asserted (if TIE = 1). To de-assert the interrupt, the TF bit or the TIE bit must be reset. Disabling the interrupt by clearing the TIE bit will de-assert the output, but does not clear the TF bit. Thus, if TIE is re-enabled prior to clearing TF, the interrupt will assert immediately.
3.8.4
Timer enable (TE)

TE = 0 When the timer register (10h) is set to 0, the timer is disabled. TE = 1 The timer is enabled. TE is reset (disabled) on power-down. When re-enabled, the counter will begin counting from the same value as when it was disabled.
3.8.5
TD1/0
These are the timer source clock frequency selection bits (see Table 12). These bits determine the source clock for the countdown timer (see Table 10 on page 36). When not in use, the TD1 and TD0 bits should be set to 11 (1/60 Hz) for power saving. Table 12. Timer source clock frequency selection (244.1 s to 4.25 hrs)
TD1 0 0 1 1 TD0 0 1 0 1 Timer source clock frequency (Hz) 4096 (244.1 s) 64 (15.6 ms) 1 (1 s) 1/60 (60 s)
3.9
Square wave output (M41T83 only)
The M41T83 offers the user a programmable square wave function which is output on the SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These frequencies are listed in Table 13. Once the selection of the SQW frequency has been completed, the SQW pin can be turned on and off under software control with the square wave enable bit (SQWE) located in register 0Ah.
Note:
If the SQWE bit is set to '1' and VCC falls below the switchover (VSO) voltage, the square wave output will be disabled.
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Clock operation Table 13. Square wave output frequency
Square wave bits RS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
M41T82-M41T83
Square wave Frequency None 32.768 8.192 4.096 2.048 1.024 512 256 128 64 32 16 8 4 2 1 Units - kHz kHz kHz kHz kHz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz
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Clock operation
3.10
Battery low warning
The M41T8x automatically checks the battery each time VCC powers up and each time the clock rolls over at midnight. VBAT is compared to VBL (approximately 2.5 V), then the battery low (BL) bit, D4 of flags register 0Fh, is set if the battery voltage is found to be less than VBL. Similarly, if VBAT is greater than VBL, the BL bit is cleared during battery check. The BL bit retains its state until the next battery check occurs. This means the BL bit will not clear immediately upon battery replacement, but only after the next battery check occurs at the next power-up or midnight rollover. If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 volts and may not be able to maintain data integrity. Clock data should be considered suspect and verified as correct. A fresh battery should be installed. If a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal VCC is supplied. In order to ensure data integrity during subsequent periods of battery backup mode, the battery should be replaced.
Midnight rollover check
As shown in Figure 22, during the midnight rollover check, the M41T8x applies a load to the battery, then compares VBAT to VBL and updates the BL bit accordingly. Because a load is present, an open condition on the VBAT pin will result in the BL bit being set. After the check is performed, the RTC removes the load.
Power-up battery check
During the power-up check, no load is applied to the battery under the assumption the battery has already been stressed to its working level by having powered the RTC in backup mode. If no battery is present, VBAT will be floating and the battery check result will be indeterminate. Figure 22. Battery check
At power-up and at rollover
VBAT
Only at rollover
VBL=2.5V
S Q FF R
BL
RL
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Clock operation
M41T82-M41T83
The M41T8x only checks the battery when powered by VCC. It does not check the battery while in backup mode. Thus, users are advised that during long periods in backup mode, the battery can drop to a level at which timekeeping may fail or data becomes corrupted. If, at power-up, a battery low is indicated, data integrity should be verified.
Forcing a battery check
If it is desired to check the battery at an arbitrary time, one common technique is for the application software to write the time to just before midnight, 23:59:59, and then wait two seconds thereby letting the clock rollover and causing the BL bit to update. The application then restores the time back to its previous value plus two seconds.
3.11
Century bits
These two bits will increment in a binary fashion at the turn of the century, and handle all leap years correctly. See Table 14 for additional explanation. Table 14. Century bits examples
CB1 0 1 0 1 Leap Year? Yes No No No Example(1) 2000 2100 2200 2300
CB0 0 0 1 1
1. Leap year occurs every four years (for years evenly divisible by four), except for years evenly divisible by 100. The only exceptions are those years evenly divisible by 400 (the year 2000 was a leap year, year 2100 is not).
3.12
Oscillator fail detection
If the oscillator fail (OF) bit is internally set to a '1,' this indicates that the oscillator has either stopped, or was stopped for some period of time. This bit can be used to judge the validity of the clock and date data. This bit will be set to '1' any time the oscillator stops. In the event the OF bit is found to be set to '1' at any time other than the initial power-up, the STOP bit (ST) should be written to a '1,' then immediately reset to 0. This will restart the oscillator. The following conditions can cause the OF bit to be set:
The first time power is applied (defaults to a '1' on power-up).
Note:
If the OF bit cannot be written to '0' four seconds after the initial power-up, the STOP bit (ST) should be written to a '1,' then immediately reset to 0.

The voltage present on VCC or battery is insufficient to support oscillation. The ST bit is set to '1.' External interference of the crystal
For the M41T83, if the oscillator fail interrupt enable bit (OFIE) is set to a '1,' the IRQ1/FT/OUT pin will also be asserted (see Section 3.13 and Section 3.14 for additional conditions which apply). The IRQ1/FT/OUT output is de-asserted by resetting the OF bit to 0, NOT by reading the flags register. The OF bit will remain a '1' until written to 0. Reading the flags register has no effect on OF.
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Clock operation
The oscillator must start and have run for at least 4 seconds before attempting to reset the OF bit to 0. The oscillator fail detect circuit funtions during backup mode. If a triggering event occurs to disrupt the oscillator during a power-down condition, the OF bit will be set accordingly.
3.13
Oscillator fail interrupt enable (M41T83 only)
With the OFIE bit set, the OF bit will cause the IRQ1/FT/OUT output to be asserted (see Section 3.14.1 and 3.14.2 for additional conditions that apply). The IRQ1/FT/OUT output is cleared by resetting the OF bit to 0 (NOT by reading the flags register). Clearing the OFIE bit will also cause the IRQ1/FT/OUT output to de-assert, but if OFIE is subsequently set prior to clearing OF, the IRQ1/FT/OUT output will assert immediately upon setting OFIE. Clearing the OF bit is necessary to prevent such an inadvertent interrupt. If the alarm in backup enable bit, ABE, is set (along with OFIE), the oscillator fail detect will cause an interrupt in the IRQ1/FT/OUT pin during backup mode. For additional information on this, refer to Section 3.14.2.
3.14
IRQ1/FT/OUT pin, frequency test, interrupts and the OUT bit (M41T83 only)
Four interrupt sources, the frequency test function, and the discrete output bit OUT all share the IRQ1/FT/OUT pin. Priority is built into the part such that some functions dominate others. Additionally, the priority depends on configuration bits such as OUT and ABE, and on whether the part is operating on VCC or is in the backup mode. This pin is an open drain output and requires an external pull-up resistor. Figure 23 shows the various signal sources and controlling bits for the IRQ1/FT/OUT output pin.
Figure 23. IRQ1/FT/OUT output pin circuit
TIMER TE reload TF TI/TP
TIE OUT FT ABE
IRQ1/OUT/FT LOGIC IRQ1/OUT/FT
Write OF to 0 to clear Read FLAGS register to clear
OF OFIE
A1IE OFIE TIE w-dog running
AF1 AI1E
WDF
Write watchdog register to clear
PRE Q
WDOG
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Clock operation
M41T82-M41T83
The timer, oscillator fail detect circuit, alarm 1, and watchdog are ORed together as the primary interrupt sources. The frequency test signal, FT, is used to enable a 512 Hz output on the IRQ1/FT/OUT pin for calibrating the RTC. When not used as an interrupt or frequency test output, the pin can be used as a discrete logic output controlled by the OUT bit. The ABE bit is used to enable interrupts during backup mode. Operating on VCC, all four interrupt sources are available. During backup, the timer and watchdog are disabled, and the only interrupt sources are alarm 1 and the oscillator fail detect circuit.
3.14.1
Active mode operation on VCC
On VCC, the operation of the output circuit is as shown in Table 15.
Table 15.
Priority for IRQ1/FT/OUT pin when operating on VCC
A1IE(3) + OFIE(4) + TIE(5) + watchdog(6) running x x 512 Hz 0 1 0 IRQ 1
OUT(1)
FT(2)
Pin
Comment
0 0 x 1 1
0 1 1 x 0
0
When OUT is 0 and FT is not enabled, OUT dominates and none of the interrupt sources have any effect. When FT = 1 and OUT = 1 and no interrupts are enabled, the output will be the 512 Hz frequency test (FT) signal. When one or more interrupts are enabled, and OUT is a 1, the pin stays high until one of the interrupts is asserted. When OUT is 1, FT is 0 and no interrupts are enabled, the pin is high.
1. OUT is bit 7 of register 08h (digital calibration). 2. FT is bit 6 of register 08h (digital calibration). 3. A1IE is bit 7 of register 0Ah (alarm 1, month). 4. OFIE is bit 7 of register 09h (watchdog). 5. TIE is bit 5 of register 11h (timer control). 6. The watchdog is controlled by register 09h (watchdog).
When OUT is 0 and FT is 0, the pin will be 0 regardless of whether any interrupts are enabled. When FT is a 1, the 512 Hz signal will be output if OUT is 0 or if no interrupts are enabled. The interrupt sources control the pin when OUT is 1 and one or more of the interrupts are enabled. If OUT is 1, FT is 0 and no interrupts are enabled, then the pin will be 1.
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Clock operation
3.14.2
Backup mode
In backup mode, the operation of the output circuit is as shown in Table 16.
Table 16.
OUT(1) x
Priority for IRQ1/FT/OUT pin when operating in backup mode
ABE(2) 0 A1IE(3) + OFIE(4) x Pin 1 Comment When ABE is 0, the pin is 1 regardless of OUT or the interrupt sources. When OUT is 1 and no interrupts are enabled, the pin is 1. (A1IE and OFIE are the only interrupts applicable in this mode). When ABE is 1 and OUT is 0, OUT dominates and regardless of the interrupt sources. When one or more interrupts are enabled, ABE is a 1, and OUT is a 1, the pin stays high until one of the interrupts is asserted.
1
x
0
1
0
1
x
0
1
1
1
IRQ
1. OUT is bit 7 of register 08h (digital calibration). 2. ABE is bit 5 of register 0Ah (alarm 1, month). 3. A1IE is bit 7 of register 0Ah (alarm 1, month). 4. OFIE is bit 7 of register 09h (watchdog).
In backup mode, frequency test is disabled. Thus, the FT bit is a `don't care'. ABE enables interrupts in backup. If it is 0, the output pin is a 1 regardless of the other bits. The pin is also a 1 when OUT is a 1 and no interrupts are enabled. When OUT is 0 and ABE is a 1, the pin is 0 regardless of the interrupts. Thus, in order to enable interrupts in backup mode, OUT must be a 1 and ABE must be a 1, and one or more of the interrupt enables must be a 1.
Simultaneous interrupts
Since more than one interrupt source can cause the IRQ1/FT/OUT pin to go low, more than one interrupt may be pending when the microprocessor services the interrupt. Therefore, the application software should read the flags register (0Fh) to discern which condition or conditions are causing the pin to be asserted. Also be aware that once a flag causes the pin to assert, other flags could subsequently also go true. Since the pin is already low due to the first, no additional output transition will occur. That is why the software must check the flags register. Example: If the watchdog is in use and the oscillator fail detect interrupt is enabled, and the watchdog times out, the IRQ1/FT/OUT pin will go low. If, in the intervening time before the processor services the interrupt, something disturbs the oscillator, such as a drop of moisture landing on the crystal pins, the OF bit will also be set. Thus, when the software services the interrupt, it must service both sources: it must re-initialize the watchdog and clear the OF bit in order to de-assert the IRQ1/FT/OUT pin. By reading the flags register, the software will know both flags were set and that both need service.
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Clock operation
M41T82-M41T83
3.15
FT/RST pin, frequency test and reset output pin (M41T82 only)
On the M41T82, the 512 Hz frequency test signal and the reset output share the same pin, FT/RST. When the FT bit (bit 6 of register 08h) is a 1, the 512 Hz test signal is activated on the pin. With FT a 0 and VCC good (above VRST), the output will be high. If the 512 Hz is enabled when VCC fails, the FT bit will be cleared and the output will go low to assert reset. At power-up, FT will be 0 leaving the pin functioning as the reset output.
3.16
Initial power-on defaults
Upon initial application of power to the device, the register bits will initially power-on in the state indicated in Table 17 and Table 18.
Table 17.
Condition(1) Initial power-up
Initial power-on default values (part 1)
ST CB1 CB0 OUT FT WatchDCS Digital Analog OFIE(2) A1IE (2) SQWE(2) ABE dog(3) ACS calib. calib. 0 UC 0 UC 0 UC 0 UC 0 0 0 UC 1 UC 0 UC
0
0 UC
0 UC
1 UC
0 0
Subsequent UC power-up(4)(5)
1. All other control bits power-up in an undetermined state. 2. M41T83 only 3. BMB0-BMB4, RB0, RB1 4. With battery backup 5. UC = unchanged
Table 18.
Condition(1) Initial power-up
Initial power-up default values (part 2)
RPT11 HT OF TE -15 0 UC 1 1 1 UC 0 0 TI/TP
(2)
TIE(2) TD1 TD0 RS0 RS1-3
OTP
(2)
A2IE(2)
RPT21AL2E 25 0 UC 0 UC
0 UC
0 UC
1 UC
1 UC
1 UC
0 UC
0 UC
0 UC
Subsequent power-up(3)(4)
1. All other control bits power-up in an undetermined state. 2. M41T83 only 3. With battery backup 4. UC = unchanged
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Clock operation
3.17
OTP bit operation (M41T83 in SOX18 package only)
When the OTP (one time programmable) bit is set to a '1,' the value in the internal OTP registers will be transferred to the analog calibration register (12h) and are "Read only." The OTP value is programmed by the manufacturer, and will contain the calibration value necessary to achieve 5 ppm at room temperature after two SMT reflows. This clock accuracy can then be guaranteed to drift no more than 3 ppm the first year, and 1 ppm for each following year due to crystal aging. If the OTP bit is set to 0, the analog calibration register will become a WRITE/READ register and function like standard SRAM memory cells, allowing the user to implement any desired value of analog calibration. When the user sets the OTP bit, they need to wait for approximately 8 ms before the analog registers transfer the value from the OTP to the analog registers due to the OTP read operation.
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Maximum ratings
M41T82-M41T83
4
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 19.
Sym TSTG VCC
Absolute maximum ratings
Parameter Storage temperature (VCC off, oscillator off) Supply voltage QFN16 Value(1) -55 to 125 -0.3 to 7.0 260(2) C 240(3) -0.2 to VCC+0.3 20 1 QFN16 35.7 128.4 C/W V mA W Unit C V
TSLD
Lead solder temperature for 10 seconds
SO8 SOX18
VIO IO PD JA
Input or output voltages Output current Power dissipation
Thermal resistance, junction to ambient
SO8 SOX18
1. Data based on characterization results, not tested in production. 2. Reflow at peak temperature of 260 C. The time above 255 C must not exceed 30 seconds. 3. Reflow at peak temperature of 240 C. The time above 235 C must not exceed 20 seconds.
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DC and AC parameters
5
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 20. Operating and AC measurement conditions
Parameter(1) Supply voltage (VCC) Ambient operating temperature (TA) Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages
1. Output Hi-Z is defined as the point where data is no longer driven.
M41T8x 2.38 V to 5.5 V -40 to 85 C 50 pF 5 ns 0.2 VCC to 0.8 VCC 0.3 VCC to 0.7 VCC
Figure 24. Measurement AC I/O waveform
0.8VCC 0.7VCC 0.3VCC
AI02568
0.2VCC
Table 21.
Symbol CIN COUT(3) tLP
Capacitance
Parameter(1)(2) Input capacitance Output capacitance Low-pass filter input time constant (SDA and SCL) Min Max 7 10 50 Unit pF pF ns
1. Effective capacitance measured with power supply at 3.6 V; sampled only, not 100% tested. 2. At 25 C, f = 1 MHz 3. Outputs deselected
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DC and AC parameters Table 22.
Sym
M41T82-M41T83
DC characteristics
Parameter Test condition(1) -40 to 85 C -40 to 85 C -40 to 85 C 0V VIN VCC 0V VOUT VCC 5.5 V 125 55 45 8 6.5 -0.3 0.7VCC RST, FT/RST VCC/VBAT = 3.0 V, IOL = 1.0 mA VCC = 3.0 V, IOL = 1.0 mA VCC = 3.0 V, IOL = 3.0 mA 2.4 5.5 2.0 2.5 25 C; VCC = 0 V; OSC on; VBAT = 3 V; 32 KHz off 365 450 5.5 0.3VCC VCC+0.3 0.4 0.4 0.4 10 SCL = 400 kHz (No load) Min 3.00 2.70 2.38 Typ Max 5.50 5.50 5.50 1 1 150 Unit V V V A A A A A A A V V V V V V V V V nA
Operating voltage (S) VCC Operating voltage (R) Operating voltage (Z) ILI ILO Input leakage current Output leakage current
ICC1
Supply current
3.0 V 2.5 (Z only)
ICC2
SCL = 0 Hz; All inputs VCC - 0.2 V or Supply current (standby) VSS + 0.2 V (SQWE bit = 0) Input low voltage Input high voltage
5.5 V 3.0 V
VIL VIH
VOL
Output low voltage
SQW, IRQ1/FT/OUT, IRQ2 SCL, SDA
VOH
Output high voltage Pull-up supply voltage (open drain)
VCC = 3.0 V, IOH = -1.0 mA (push-pull) IRQ1/FT/OUT, IRQ2, FT/RST, RST
VBAT VBL IBAT
Backup supply voltage (battery or capacitor) Battery low (BL bit) threshold Battery supply current
1. Valid for ambient operating temperature: TA = -40 to 85 C; VCC = 2.38 V to 5.5 V (except where noted)
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M41T82-M41T83 Figure 25. ICC2 vs. temperature
10.000
DC and AC parameters
9.000
8.000
7.000 Icc2 (A) (3.0V) (5.0V)
6.000
5.000
4.000
3.000
2.000 -40
-20
0
20 Temperature (C)
40
60
80
ai 13909
Table 23.
Symbol fO RS CL
Crystal electrical characteristics
Parameter(1)(2) Resonant frequency Series resistance Load capacitance 12.5 Min Typ 32.768 65(3) Max Units kHz k pF
1. Externally supplied if using the QFN16 or SO8 package. STMicroelectronics recommends the Citizen CFS145 (1.5 x 5 mm) and the KDS DT-38 (3 x 8 mm) for thru-hole, or the KDS DMX-26S (3.2 x 8 mm) or Micro Crystal MS3V-T1R (1.5 x 5 mm) for surface-mount, tuning fork-type quartz crystals. For contact information, see Section 8: References on page 59. 2. Load capacitors are integrated within the M41T8x. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account. 3. Guaranteed by design.
Table 24.
Symbol VSTA tSTA CXI, CXO(1)
Oscillator characteristics
Parameter(1)(2) Oscillator start voltage Oscillator start time Capacitor input, capacitor output IC-to-IC frequency variation(2)(3) -10 Conditions 4s VCC = VSO 25 +10 Min 2.0 1 Typ Max Units V s pF ppm
1. With default analog calibration value ( = 0) 2. Reference value 3. TA = 25 C, VCC = 5.0 V
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DC and AC parameters Figure 26. Power down/up mode AC waveforms
VCC VSO VRST
M41T82-M41T83
trec SDA, SCL tRD RST
AI00596
DON'T CARE
Table 25.
Sym
Power down/up trip points DC characteristics
Parameter(1)(2) S Min 2.85 2.55 2.25 Typ 2.93 2.63 2.32 VRST 25 140 2.5 280 Max 3.0 2.7 2.38 Unit V V V V mV ms s
VRST
Reset threshold voltage
R Z
Battery backup switchover VSO trec tRD Hysteresis RST duration after VCC high VCC to reset delay(3)
1. All voltages referenced to VSS 2. Valid for ambient operating temperature: TA = -40 to 85 C; VCC = 2.38 to 5.5 V (except where noted) 3. Measured with VCC falling slew rate of 10 mV/s for VCC in the range VRST + 100 mV to VRST - 100 mV
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M41T82-M41T83 Figure 27. Bus timing requirement sequence
DC and AC parameters
SDA tBUF tHD:STA tR SCL tHIGH P S tLOW tSU:DAT tHD:DAT tSU:STA SR P
AI00589
tHD:STA tF
tSU:STO
Table 26.
Sym fSCL tLOW tHIGH tR tF tHD:STA tSU:STA
AC characteristics
Parameter(1) SCL clock frequency Clock low period Clock high period SDA and SCL rise time SDA and SCL fall time START condition hold time (after this period the first clock pulse is generated) START condition setup time (only relevant for a repeated start condition) 600 600 100 0 600 1.3 Min 0 1.3 600 300 300 Typ Max 400 Units kHz s ns ns ns ns ns ns s ns s
tSU:DAT(2) Data setup time tHD:DAT tSU:STO tBUF Data hold time STOP condition setup time Time the bus must be free before a new transmission can start
1. Valid for ambient operating temperature: TA = -40 to 85 C; VCC = 2.38 to 5.5 V (except where noted). 2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of SCL.
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Package mechanical data
M41T82-M41T83
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark.
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Package mechanical data
Figure 28. QFN16 - 16-lead, quad, flat package, no lead, 4 x 4 mm body size outline
D
E
A3
A1
A
ddd C
b L
e
1 2
E2
3
D2
QFN16-A
Note:
Drawing is not to scale. Table 27.
Sym Typ A A1 A3 b D D2 E E2 e L ddd 0.90 0.02 0.20 0.30 4.00 - 4.00 - 0.65 0.40 - Min 0.80 0.00 - 0.25 3.90 2.50 3.90 2.50 - 0.30 0.08 Max 1.00 0.05 - 0.35 4.10 2.80 4.10 2.80 - 0.50 - Typ 0.035 0.001 0.008 0.012 0.157 - 0.157 - 0.026 0.016 - Min 0.031 0.000 - 0.010 0.154 0.098 0.154 0.098 - 0.012 0.003 Max 0.039 0.002 - 0.014 0.161 0.110 0.161 0.110 - 0.020 -
QFN16 - 16-lead, quad, flat package, no lead, 4 x 4 mm pack. mech. data
mm inches
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Package mechanical data
M41T82-M41T83
Figure 29. QFN16 - 16-lead, quad, flat package, no lead, 4 x 4 mm, recommended footprint
2.70 0.70 0.20
4.50
2.70
0.35 0.325 0.65
AI11815
Note:
Dimensions are shown in millimeters (mm). Figure 30. 32 KHz crystal + QFN16 vs. VSOJ20 mechanical data
6.0 0.2
3.2 VSOJ20
1.5
SMT CRYSTAL
7.0 0.3
15 XI 16 XO 14 13 1
3.9
2 3 4
ST QFN16
3.9
AI11816
Note:
Dimensions shown are in millimeters (mm).
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Package mechanical data
Figure 31. SOX18 - 18-lead plastic small outline, 300 mils, embedded crystal, outline
SOX18
Note:
Drawing is not to scale. Table 28. SOX18 - 18-lead plastic small outline, 300 mils, embedded crystal, package mech. data
millimeters Symbol Typ A A1 A2 B c D E E1 e L 2.57 0.23 2.34 0.46 0.25 11.61 7.62 10.34 1.27 0.66 Min 2.44 0.15 2.29 0.41 0.20 11.56 7.57 10.16 - 0.51 Max 2.69 0.31 2.39 0.51 0.31 11.66 7.67 10.52 - 0.81 Typ 0.101 0.009 0.092 0.018 0.010 0.457 0.300 0.407 0.050 0.026 Min 0.096 0.006 0.090 0.016 0.008 0.455 0.298 0.400 - 0.020 Max 0.106 0.012 0.094 0.020 0.012 0.459 0.302 0.414 - 0.032 inches
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Package mechanical data Figure 32. SO8 - 8-lead plastic small package outline
h x 45 A2 b e 0.25 mm GAUGE PLANE k
8
M41T82-M41T83
A ccc c
D
E1
1
E A1 L L1
SO-A
Note:
Drawing is not to scale. Table 29. SO8 - 8-lead plastic small outline (150 mils body width), package mech. data
mm Symb Typ A A1 A2 b c ccc D E E1 e h k L L1 1.04 4.90 6.00 3.90 1.27 4.80 5.80 3.80 0.25 0 0.40 0.10 1.25 0.28 0.17 0.48 0.23 0.10 5.00 6.20 4.00 0.50 8 0.127 0.041 0.193 0.236 0.154 0.050 0.189 0.228 0.150 0.010 0 0.016 Min Max 1.75 0.25 0.004 0.049 0.011 0.007 0.019 0.009 0.004 0.197 0.244 0.157 0.020 8 0.050 Typ Min Max 0.069 0.010 inches
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M41T82-M41T83 Figure 33. Carrier tape for QFN16, SOX18, and SO8 packages
Package mechanical data
P0 D T P2
E
A0 TOP COVER TAPE B0
F W
K0
CENTER LINES OF CAVITY
P1
USER DIRECTION OF FEED
AM03073v1
Table 30.
Package
Carrier tape dimensions for QFN16, SOX18, and SO8 packages
W 12.00 0.30 24.00 0.30 12.00 0.30 D 1.50 +0.10/ -0.00 1.50 +0.10/ -0.00 1.50 +0.10/ -0.00 E P0 P2 F A0 4.30 0.10 12.70 0.10 6.50 0.10 B0 4.30 0.10 11.90 0.10 5.30 0.10 K0 1.10 0.10 3.20 0.10 2.20 0.10 P1 8.00 0.10 16.00 0.10 8.00 0.10 T 0.30 0.05 0.30 0.05 0.30 0.05 Unit Bulk Qty
QFN16
1.75 4.00 2.00 5.50 0.10 0.10 0.10 0.05 1.75 4.00 2.00 11.50 0.10 0.10 0.10 0.10 1.75 4.00 2.00 5.50 0.10 0.10 0.10 0.05
mm 1000
SOX18
mm 1000
SO8
mm 2500
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Part numbering
M41T82-M41T83
7
Part numbering
Table 31.
Example:
Ordering information
M41T 83 S QA 6 E
Device family M41T
Device type 82 (SO8 package only) 83
Operating voltage S = VCC = 3.00 to 5.5 V R = VCC = 2.70 to 5.5 V Z = VCC = 2.38 to 5.5 V
Package QA = QFN16 (4 mm x 4 mm) M(1) = SO8 MY(2)= SOX18
Temperature range 6 = -40 C to 85 C
Shipping method E = ECOPACK(R) package, tubes F = ECOPACK(R) package, tape & reel
1. M41T82 only 2. The SOX18 package includes an embedded 32,768 Hz crystal.
For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you.
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References
8
References
Below is a listing of the crystal component suppliers mentioned in this document.

KDS can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp. Citizen can be contacted at csd@citizen-america.com or http://www.citizencrystal.com. Micro Crystal can be contacted at sales@microcrystal.ch or http://www.microcrystal.com.
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Revision history
M41T82-M41T83
9
Table 32.
Date
Revision history
Document revision history
Revision Changes Updated Table 1, 2, 4, 6, 10, 11, 22, Figure 19, 26, Section 3, Section 3.4.1, Section 3.4.2, Section 3.5, Section 3.6, Section 3.7, Section 3.8, Section 3.8.2, Section 3.8.3, Section 3.8.4, Section 3.8.5, Section 3.12, Section 3.13, Section 6; added Section 3.8.1, Section 3.14, Section 3.15, Table 9, 15, 16, Figure 21, 23; removed "output driver pin" section, "alarm interrupt reset waveform" figure, "backup mode alarm waveform" figure, "timer countdown value register bits (addr 11h)" table; added tape and reel information Figure 33, Table 30. Updated Section 2.2: Read mode, Section 2.3: Write mode, Section 3: Clock operation, Section 3.1: Power-down time-stamp, Section 3.2: Clock/control register map and divider chain, Table 26. Updated Figure 26; Table 25. Updated Note in Section 3.12: Oscillator fail detection.
09-Apr-2009
9
05-Jan-2010 25-Mar-2010 19-Oct-2010
10 11 12
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